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This paper presents a dual-gate junctionless FET (DGJLT) on SOI for enhanced analog/RF performance. ormas pp The Si channel of device is sandwiched between the two gates placed in separate vertical trenches. pp wa kosong estetik The proposed structure is studied for moderately doped drain (MDD) and heavily doped drain (HDD) concentrations The analog/RF performance parameters of both the configurations are analysed and